Temperature dependent leakage power characteristics of dynamic circuits in sub-65 nm CMOS technologies

The temperature dependent subthreshold and gate oxide leakage power characteristics of domino logic circuits are evaluated in this paper. The preferred input vectors and node voltage states that minimize the total leakage power consumption are identified at the lower and upper extremes of a typical die temperature spectrum. New low leakage circuit design guidelines are presented based on the results. The significantly increased gate dielectric tunneling current, as described in this paper, dramatically changes the leakage power characteristics of dynamic circuits in the sub-65nm CMOS technologies. Furthermore, the leakage power savings provided by the dual threshold voltage domino logic circuit techniques are all together reduced due to the significance of the gate dielectric tunneling in the nanometer CMOS technologies.