ESD protection circuit with an improved ESD capability for input or output circuit protection

An ESD protection circuit in chip level protection is proposed as the electrostatic discharge (ESD) clamping circuit such as thick field oxide (TFO), grounded gate MOS (GGNMOS) and separated stages for input or output protection. The ESD protection circuits for input pad and output pad were implemented from the proposed ESD protection circuit. The realized protection circuits for input pad and output pad have been simulated by HSPICE and approved the improved ESD capability.