Design strategies of cascaded CML gates

In this paper, a strategy to design paths consisting of cascaded bipolar current-mode logic gates is proposed. In particular, explicit design criteria are derived both for low-power non-critical paths and high-speed critical paths. The analytical results are simple to be applied to actual circuits avoiding the usual time-consuming approach based on iterative simulations with a trial-and-error procedure. Moreover, it provides the designer with a deeper understanding of the power-delay trade-off. Design examples based on a 20-GHz bipolar process are introduced to validate the procedure and clarify its application.