Architecture for 2-D IDCT for real time decoding of MPEG/JPEG compliant bitstreams

In this paper, architecture for hardware implementation of 2-dimensional inverse discrete cosine transform (2-D IDCT) is described. The architecture is based on a recursive algorithm, which implements the 2-D operation using a series of 1-D operations. Pipelining/interleaving technique is employed in our recursive computing scheme to overcome the clock rate limitation in recursive computation and to reduce the number of multipliers and clock cycles. More specifically, we are able to make the processing speed remain nearly invariant by using a higher clock rate, while the number of non-trivial multipliers is reduced by half. Furthermore, the cosine terms involved in the digital filter coefficients are pre-calculated and are implemented as fixed coefficient CSD multipliers. Although this reduces the flexibility in the architecture for supporting different block sizes, but this cost pays off due to the high gain in the computational efficiency of fixed coefficient CSD multipliers. Using architectural schemes like pipelining/interleaving, the computation of an 8/spl times/8 IDCT block is completed in just 209 clock cycles. This can be used with an external microcontroller for displaying JPEG images in cell phone displays, where stored images in JPEG format only need to be decoded for display.