A high-frequency nonquasi-static analytical model including gate leakage effects for on-chip decoupling capacitors

This paper presents a compact model for on-chip decoupling capacitors (decaps) including gate-oxide leakage. The model makes use of only four parameters, namely, channel resistance, gate-oxide capacitance, and two parameters to quantify gate-oxide leakage, to predict the static and dynamic response of decaps. Quality indices have been defined to enable development of decap design guidelines and evaluation of performance of such capacitors. The model shows how the gate leakage and longer channel lengths severely affect the performance of on-chip decaps for both low and high frequencies. The model also shows that lumped models of decaps at high frequencies fail and have to be substituted by a distributed model. Application of the model uncovers tradeoffs for thin- and thick-oxide capacitors in an available 90-nm CMOS technology. For a general-purpose technology, a reference capacitance value has been realized using decaps with a discrete width and length. Our model predicts that thick-oxide n-channel (p-channel) capacitors require /spl sim/3.37x (/spl sim/3.31x) more silicon area and /spl sim/1.70x (/spl sim/1.17x) degraded time response as compared to their thin-oxide versions. The time response is even more degraded (/spl prop/L/sup 2/) when longer channel decaps are used. This paper contributes by defining performance benchmarks for decaps.