A Design Rule Independent Cell Compiler

To achieve fast turn around, appropriate performance and efficient silicon area in ASIC design, it is desirable to have the capability of generating new customized cells overnight. A design rule independent cell compiler which is capable of generating nearly optimal layout and all the desirable user interfaces such as automatic place and route database, data sheet, SPICE information and the layout verification model for any user specified cell is reported in this paper. The algorithms used for cell synthesis are also discussed in this paper.