A self-timed structural test methodology for timing anomalies due to defects and process variations

We present a new structural self-timed delay test methodology that identifies timing anomalies in the circuit by comparing the relative switching time of the different signal lines feeding the scan chains. These are observed by capturing the circuit's response to a delay test at multiple sample times, at and below the design cycle time. A timing defect is detected if there is a reversal in the switching order of any two outputs from that reliably predicted by simulation (or measurement on golden circuits), while allowing for processes variations