An optimum hardware detector for constant envelope quadrature-quadrature phase-shift keying (CEQ/sup 2/PSK)

A hardware detector for constant envelope quadrature-quadrature phase-shift keying (CEQ/sup 2/PSK) is proposed. It uses appropriate hard decisions; yet, it achieves optimum probability of bit error performance, unlike the suboptimum detector of Saha and Birdsall. This optimum performance is verified through Monte Carlo computer simulations. Additionally, a more correct expression is given for the probability of bit error performance for CEQ/sup 2/PSK, which gives the gain over nonconstant Q/sup 2/PSK as 1.44 dB, rather than the previously published value of 1.76 dB.