Mapping matrix-vector multiplication algorithm onto fault-tolerant unidirectional systolic array

In this paper we design a unidirectional linear systolic array (ULSA) for fault-tolerant matrix-vector multiplication. We first derive a systolic algorithm which is suitable for ULSA synthesis. Then we modify this algorithm in order Io obtain ULSA with optimal number of processing elements. Finally, redundancies are introduced at computational level by deriving three equivalent algorithms but with disjoint index spaces. The obtained algorithm is then used to design space-optimal fault-tolerant ULSA. Fault-tolerance is achieved by triplicated computation and majority voting. By the proposed scheme single transient errors can be tolerated.