Challenge: variability characterization and modeling for 65- to 90-nm processes

In sub-100-nm processes, many physical phenomena have become critical issues in the development of processes, devices, and circuits. To achieve reasonable compromise in ASIC design, device-and process-level characterization of physical designs is a fundamental requirement. In this paper, we address topics regarding "design for variability", which are increasingly important in the 65- to 90-nm technology era. We have developed a new test-structure to precisely measure the on-chip variation of key LSI components (MOST, R, C, and circuit-delay). Statistical analysis of the experimental results revealed that the 3/spl sigma/ variation of MOS drive-current within a chip was 30%, which led to equal variation in the circuit propagation delay (Tpd). We found that variation can be suppressed due to its randomness features in multi-stage circuitry and high-performance, large-gate-area driver CMOS devices.