Packet switch using reconfigurable optical central crossbars

This paper will discuss a packet switch demonstrator, which is being implemented on separate programmable logic devices forming electronic "islands" interconnected by a reconfigurable central stage crossbar with the capability of emulating optical link delay. The current design will have 8 inputs and 8 outputs and each sector will be a 4/spl times/4 sub-switch implemented on a single field-programmable gate array (FPGA) with shared buffer memory. Communication among modules within the demonstrator is performed through a custom high speed 10Mbps interface.