Implementation and simulation of a cluster-based hierarchical NoC architecture for multi-processor SoC

Future high-end SoC applications will require huge computation and communication capabilities, which are provided by multiple processing cores integrated by on-chip communication architecture. Network-on-chip (NoC) provides a structured way of realizing inter-core communications on silicon for highly parallel SoC. The design of our CHNoC (cluster-based hierarchical NoC) architecture is presented, together with simulation results. It provides scalable interconnection for hundreds of cores and clusters. An MPEG-4 decoder on our architecture illustrates the performance and feasibility of CHNoC.