Smart PCBs manufacturing technologies

The inherent functionality of a printed wiring board can be dramatically increased by embedding electronic components into the board. For resistors, capacitors and inductors technological turnkey solutions are offered by major manufacturers and also technologies are under development. Application examples for passives integration into flexible PCBs are given. A further boost of functionality is accomplished by the integration of active chips into the board. An overview of different approaches and the respective sets of enabling technologies for the integration of chips into the board are given. Two of the approaches for the chip integration into the board are discussed in detail. A prerequisite for those technologies is the chip thinning, which is now available as a commercial service for chip thicknesses down to 20 /spl mu/m. In the chip in polymer (CIP) approach the thin chip is precisely positioned and soundly attached onto the board surface. After lamination of a copper coated resin foil via contacts are drilled through the laminate to the contact pads of the chip. The transfer of precise chip position parameters with respect to the board is essential for this step. The wiring on the laminate foil to the chip and to other components is subsequently structured. Process parameters and results are presented. For the embedding of chips into flexible PCBs the chip is flipped onto the substrate surface and thermode bonded. The process implies soldering. Therefore electroless Ni(P) is deposited onto the Al bond pads of the chip which is subsequently covered with small caps of solder. The solder cap heights are in the range of 4 to 8 /spl mu/m in order to keep the interconnection height low. The solder joint is realized by thermode bonding of the chip onto the structured wiring of the substrate using no-flow underfiller. The chip containing layer is then laminated and contacted to outer layers of the board by conventional through hole technique. An assessment of the advantages and disadvantages of both approaches are given on the status of our present understanding of the technological challenges.