Harmonic distortion caused by capacitors implemented with MOSFET gates

The capacitive gate structures available in digital-oriented CMOS processes are reviewed, with emphasis on their use as linear capacitors. It is shown that the voltage harmonic distortion in MOS gate capacitors biased in either accumulation or strong inversion is almost technology independent. Experimental and analytical results indicate that the total harmonic distortion in an adequately biased (2.5 V) gate capacitor can be kept low (THD <-40 dB for a 3-V voltage swing).<
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