New VHDL design of decimation filter for sigma-delta modulator

This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta (/spl sigma//spl Delta/) modulator. Parameters of decimation filter are derived from the specifications of the overall /spl sigma//spl Delta/ modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Then second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 /spl mu/m technology.