Double abstraction level heuristic power optimization for digital signal processors using GA's

In this paper the authors explored a new approach towards optimization of dedicated reconfigurable DSP processors using a two pronged approach. At the logic level, metarules are used to abstract global heuristic knowledge or particular design strategies to optimize the parent population size which are dynamically reconfigured by applying genetic algorithms. At the algorithm level, a data based probabilistic heuristic scheduling algorithm incorporating pipelining was proposed, resulting in resource optimization that adapts to programmable infrastructure with better speed, cost and power dissipation compared to GPP especially in image processing and signal processing tasks. This paper proposes an alternative approach to power-minimization based on a dynamic matching between architecture and computation.