Measurement and Simulation of Interconnect Inductance in 90 nm and Beyond

The on-chip inductance impact on signal integrity has been a problem for designs in deep-submicron technologies. The impact increases clock skew, max-timing and noise levels of bus signals. In this paper, circuit macro-models are bench-marked against test chip measurement in a 90 nm technology. Circuit simulations show the inductive impact on clock skew (e.g., 1lps in 2GHz clock frequency), signal delay (e.g., 11% max-timing push-out) and noise levels (e.g., 13% VDD). In addition, the inductive impact on signal integrity in the presence of process variations is evaluated. Finally, inductive impact in 65nm and 45 nm technologies is simulated, which indicates that the inductance impact will not diminish as technology scales.