Gate resistance modeling of multifin MOS devices

This letter studies the effects of geometrical parameters (fin spacing, fin height and polysilicon thickness) on the gate resistance of multifin MOS devices. An effective lumped resistance model derived from distributed RC network is formulated and verified using a two-dimensional simulator. Based on the model, a design guideline for the fin spacing to minimize the gate resistance and RC delay is provided to design multifin MOS devices for high frequency applications.