Real time 3D rendering patch processing using an embedded SIMD computer architecture

This paper demonstrates that three dimensional imaging operations can benefit from the parallel processing provided by a single instruction multiple data (SIMD) processing array. The SIMD array used for implementation is a processor in memory architecture created by Atsana Semiconductor. This design is used in Atsana's J2210 media processor, which is used as the test platform for this project. The J2210 is a system on a chip containing an ARM/spl trade/ microprocessor and a SIMD array processor. The goal is to test this SIMD architecture for suitability as a hardware acceleration system for real time rendering of 3D scenes in an embedded platform. SIMD architectures take advantage of data parallelism, which is readily available in 3D rendering.