Effective implementation of floating-point adder using pipelined LOP in FPGAs

The current intellectual property provided by Xilinx for floating-point adder is not competitive and versatile. This paper presents a hardware implementation of IEEE 754 compliant floating-point adder and a design methodology for floating-point adder with leading-one predictor (LOP). LOP has been used to predict the shift amount for post normalization in parallel with the addition. In some cases, however, there is an error in prediction. LOP used in our design detects this error concurrently with the prediction. Xilinx 6.3 ISE was used to synthesize VHDL implementations for five levels of pipeline stage floating-point adder. LOP was pipelined to three stages, to obtain better latency for some Xilinx FPGA devices compared to the current intellectual property. For Spartan 3 and Virtex 2p FPGA architectures with five stage pipeline implementation, 25% improvement in clock speed was achieved using pipelined LOP.