On the optimization of lateral pnp BJTs found in BiCMOS process technologies

We present a comprehensive investigation aimed at optimizing the performance of lateral pnp BJTs found in BiCMOS technologies to a level suitable for analog, IF/RF circuit applications. Alternative base profiles, LDD implantations conditions, and device geometries are quantitatively assessed, as well as the path of adapting low-voltage (LV) pMOS vs. high-voltage (HV) pMOS device design points for viable lateral pnp BJTs. The resultant dc, ac and low-frequency noise characteristics are addressed.