A 100dB+ SFDR 80MSPS 14 bit 0.35/spl mu/m BiCMOS pipeline ADC

The cellular infrastructure market requires high clock rate, high dynamic range ADCs to enable efficient, advanced architecture receive channels. This paper describes a 14 bit 80MSPS ADC with 100dB+ SFDR at baseband in 0.35/spl mu/m BiCMOS technology using 1.1 watts on a 3.3V/5.0V dual supply. Some challenges associated with high spurious free dynamic range at high clock rates will be discussed along with methods used in this ADC to overcome these barriers.