Integrated assignment of registers and functional units for heterogeneous vliw-architectures

Typically, modern digital signal processors with VLIW-like architectures provide several functional units and register files. To limit the number of interconnects, register files are fully connected only to a subset of the functional units. Transferring data from arbitrary register files to functional units may be subject to bus constraints. Additionally, the set of functional units is often heterogeneous where certain operations like addition may be performed by several units while others like multiplication are limited to a single unit. Register assignment and functional unit assignment are two interdependent code generation phases for these architectures. Although both of them are hard combinatorial optimization problems, we present a combined approach that generates optimum solutions. This is achieved by a pruned search space representation based on interval graphs. Together with an adapted resource model we show the feasibility of optimum solution space exploration for current architectures like TI's C6x family