Scaling analysis of multilevel interconnect temperatures for high-performance ICs

This paper presents a comprehensive thermal scaling analysis of multilevel interconnects in deep nanometer scale CMOS technologies based on technological, structural, and material data from the International Technology Roadmap for Semiconductors. Numerical simulations have been performed using three-dimensional electrothermal finite element methods, combined with accurate calculations of temperature- and size-dependent Cu resistivity and thermal conductivity of low-/spl kappa/ interlayer dielectrics (ILD) based on fully physical models. The simulations also incorporate various scaling factors from fundamental material level to system level: the via-density-dependent effective ILD thermal conductivity, the hierarchically varying root mean square current stress based on SPICE simulations, and the thermal resistance of flip-chip package. It is shown that even after considering densely embedded vias, the interconnect temperature is expected to increase significantly with scaling, due to increasing current density, increasing surface and grain boundary contributions to metal resistivity, and decreasing ILD thermal conductivity.