An FPGA architecture design of parameter-adaptive real-time image processing system for edge detection

In this paper we present an FPGA architecture design of parameter-adaptive real-time image processing system for edge detection. The system contains two edge detection algorithms which are suitable for hardware realization and insensitive to noise. The two adopted algorithms are able to produce different outputs suitable for different applications. A controller which integrates parameter setting, continuous edge detection task processing and output selection is proposed. The proposed modified LGT algorithm not only preserves the original edge detection performance, but also greatly reduces the use of hardware resource. We adopt FPGA design flow as our early-stage verification platform, and result in a maximum working frequency of 54 MHz, which is able to process 205 512/spl times/512 grayscale images, and is 90 times faster than the software execution.