A PLL frequency multiplier for LVDS transmitter

A. 3.5 times PLL clock frequency multiplier for LVDS driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth, and a VCO is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25/spl mu/m mixed-signal CMOS process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time.