Collector optimization in advanced SiGe HBT technologies

With the advancement of the fT/fMAX performance scaling of SiGe HBTs the breakdown voltage (BVCBO/BVCEO) reduces commensurately, causing design related concerns. It is important, therefore, that multiple fT/BVCEO devices be offered in the RF technologies to meet the varying needs of the communication products. Unlike the GaAs technologies, the SiGe BiCMOS technologies are capable of integrating various flavors of fT/BVCEO SiGe HBT devices at a technology node. In this work, we investigate the tradeoff in fT-BVCEO for advanced SiGe HBTs by various collector optimization schemes such as, subcollector dopant species and concentration, epilayer thickness, SIC and other layout techniques.