Very high radix scalable Montgomery multipliers

This paper describes a very high radix scalable Montgomery multiplier. It extends the radix-2 Tenca-Kog scalable architecture using w /spl times/ v - bit integer multipliers in place of AND gates. The design can perform 1024-bit modular exponentiation in 6.6 ms using 2847 4-input lookup tables and 32 16 /spl times/ 16 multipliers, making it the fastest scalable design yet reported.