Hardware efficient LBIST with complementary weights

In this paper, a novel logic BIST (built-in self test) scheme with complementary weights is proposed. The BIST implementation combines random patterns with complementary-weight weighted patterns. A heuristic algorithm based on deterministic test set is developed to compute weight set with complementary weights. Hardware similar to bit-flipping is used to produce complementary weights. For random resistant ISCAS circuits, complete fault coverage can be achieved with very low hardware overhead. Experiments show that two complementary weights are sufficient for weighted random pattern testing and it presents a novel direction for exploiting weighted patterns.