VHDL-AMS behavioral modelling and simulation of high-pass delta-sigma modulator

High-pass /spl Delta//spl Sigma/ modulator has the advantage of immunity from the low frequency noise and is thus very effective in the parallel architectures. In this paper, we present the behavioral modelling and simulation of /spl Delta//spl Sigma/ modulators in VHDL-AMS, and in particular of the high-pass modulator. A set of models in VHDL-AMS suitable for time-domain behavioral simulation of SC /spl Delta//spl Sigma/ modulators is developed. The proposed set of models takes into account at the behavioral level most of SC /spl Delta//spl Sigma/ modulator nonidealities, such as jitter noise, kT/C noise, 1/f noise, amplifier noise, switch nonidealities, amplifier nonidealities, and capacitor mismatch. We elaborate then a top-down design methodology that is validated by the measurement results.