Low power (51 mW per flip-flop) CML static divider implemented in scaled 0.25 /spl mu/m emitter-width InP DHBTs

We report the fabrication and performance of a static CML frequency divider implemented in 0.25/spl mu/m emitter-width InP DHBT technology. This circuit consumed an average of 51 mW per flip-flop in a divide by 8 configuration while dividing a 120 GHz input. To our knowledge this is the highest toggle rate reported for circuits with power consumption as low as this.