Linearity optimization of a high power Doherty amplifier

The linearity of a 30 W high power Doherty amplifier is optimized using post-distortion compensation. A balanced high power Doherty amplifier using two push-pull LDMOS FETs is linearized by optimum adjustment of the peaking compensation line, shunt capacitors and gate biases. The optimized Doherty amplifier measured results for a 4-carrier W-CDMA signal, achieved -43 dBc ACLR at a /spl plusmn/5 MHz offset frequency. This is an ACLR improvement of 12.2 dB and 6.5 dB in comparison to the Doherty amplifier before optimization and a class AB amplifier, respectively.