Study on the power bus noise isolation using a SPICE compatible method

In nowadays high speed PCB design, the normal operation of the analog integrated circuits depends much on the stable voltage supply between DC power and ground. To maintain the signal fidelity and mitigate the effect of SSN (simultaneous switching noise) on the power signal, power bus plane segmentation and noisy device isolation using power island are often employed. This paper proposed one method that can simulate the effects of the power bus noise isolation using the SPICE compatible method to provide the strategy to the IC design.