In-chip overlay metrology in 90 nm production

We have inserted, measured and demonstrated good metrology performance on in-die overlay targets on product wafers. It is shown that scanner aberration induced pattern placement errors (PPE) can be measured, simulated and validated by CD-SEM, but the magnitude of the effect on late generation scanners is small - of the order of /spl sim/1.5 nm peak to peak across the slit. It is observed that in-die overlay data contains additional sources of variation beyond PPE and the results have been verified by SEM. It is demonstrated that current practices based on linear models do not capture in-die variations which significantly impacts model residuals. Currently, in-die target insertion is an insurance policy which enables in-die trouble shooting when process issues are suspected and will potentially improve lot dispositioning in the future.