Design of PLL system based Verilog-AMS behavior models

A top-down design method on analog PLL system based Verilog-AMS HDL behavior models is proposed. A PLL contained a VCO behavior model with center frequency 120 MHz and a two-order passive filter with cut-off frequency 300.0 KHz is implemented. The Verilog-AMS behavior models are verified and used in PLL system simulation by the tools of Cadence spectre.