5-Gb/s 0.18-/spl mu/m CMOS clock recovery circuit

A 5 Gb/s monolithic phase-locked clock recovery circuit is designed and realized in a 0.18 /spl mu/m CMOS technology. A half rate bang-bang phase detector and a multiphase oscillator incorporated with a charger-pump builds up half-rate phase-locked loop (PLL) architecture. The measured rms jitter of recovered clock signal is 4.7 ps under the stimulation of a 2/sup 11/-1-bit-long pseudorandom bit sequence at the bit rate of 5 Gb/s. The chip area is only 0.6 mm /spl times/ 0.6 mm and the DC power consumption is less than 90 mW under a single 1.8 V supply.