Nanocantilevers with integrated CMOS: effects of electron beam lithography on NMOS transistors

The effect of electron beam lithography for patterning to the nanoscale a polysilicon layer electrically connected to the gate of an NMOS transistor is studied. Different acceleration voltages ranging from 4 to 35 kV have been considered. The effect has been evaluated by measuring the transistor electrical characteristics before and after electron beam exposure. The obtained results indicate that when processing at high acceleration voltages a severe degradation of the transistor characteristics is caused that would lead to the loss of circuit performance when using this technology for the fabrication of nanocantilevers with integrated CMOS.