Design and implementation of an ASIC architecture for the context-based binary arithmetic encoder

This paper presents an area-efficient ASIC architecture for the context-based binary arithmetic encoder in JPEG2000, which is compatible with the arithmetic encoder defined in ISO/IEC 155444-1. The proposed architecture employs look-ahead computation as well as data-dependency analysis to improve the encoding performance. By exploiting these two strategies, the averaged encoding cycle time for each input symbol can be significantly reduced. According to our simulation results, for each byte of compressed data the proposed architecture spends only two clock cycles in most cases and at most five clock cycles in rare cases. Moreover, we have implemented the proposed architecture using an FPGA and successfully validated its function.