Design techniques for INL and jitter prediction of a 3.3V 16b 65MSps pipeline ADC core

This work introduces design techniques and experimental results relative to a 16b 65MSps pipeline ADC core implemented in 0.4/spl mu/m, 45GHz-fr SiGe BiCMOS. A fast methodology for simulating the INL with Spice enables the implementation of low-distortion sample/hold and quantizer at 3.3V supply and high input range (4Vpp). Accurate prediction of aperture uncertainty allow the optimization of the on-chip clock circuit, yielding 180fs RMS jitter and 73.5dBFS SNR at 150MHz input. The test chip delivers 78.3dBFS SNR, 88dBc SFDR at 65MSps, 1MHz and 970mW consumption with external voltage references.