Novel self-convergent scheme logic-process-based multilevel/analog EEPROM memory

A novel multilevel/analog electrically erasable programmable read only memory (EEPROM) cell fabricated by standard complementary metal oxide semiconductor (CMOS) logic process is presented. The cell is operated by select-gate-controlled channel current induced drain avalanche hot hole for programming and hot electron for erasing. The self-convergent programming scheme is proposed allows this cell to be easily adopted for the multilevel or analog storage. In addition, a compact SPICE sub-circuit model of the cell has been established to facilitate cell behavior simulation with its interfacing circuits, especially for multilevel/analog nonvolatile memory applications.