Switching delay variability in NMOS and PMOS PDSOI passgate circuits

Switching delays of partially-depleted SOI (PDSOI) CMOS gates are subject to variability depending on the switching history (S. Fung et al., 2000). This variability results from modulation of the threshold voltage by the floating body potential. To characterize this behavior it is important to study device response over a wide range of floating body potentials. We accomplish this by configuring NFETs and PFETs as single ended passgates driven by inverters with the input arrival times at both the source and the gate controlled independently. Representative data from a chip fabricated in an experimental 0.18 /spl mu/m PDSOI technology is presented and discussed.