Monolithic IC of SDH STM-16 optical receiver, core circuits

The design and the experimental results of a monolithic packed IC with functions of clock recovery, data decision and 1:4 demultiplexer for 2.5-Gb/s fiber-optic communications have been provided. The IC was implemented in TSMC 0.25/spl mu/m CMOS process. The capture range of the PLL is 80-MHz, the recovered and frequency divided 625-MHz clock has a phase noise of -106.26dBc/Hz at 100-kHz offset in response to 2.5-Gb/s PRBS input data (2/sup 31/-1), and the 2.5-Gb/s PRBS data have been demultiplexed to four 625-Mb/s data.