A 0.5V filter with PLL-based tuning in 0.18 /spl mu/m CMOS

Design techniques that allow analog circuit operation with supply voltages as low as 0.5V are presented. A fully integrated 135kHz fifth-order elliptic LPF, including automatic bias circuits and an on-chip PLL for tuning, is implemented with standard devices in a 0.18 /spl mu/m CMOS process. The 1mm/sup 2/ chip has a measured DR of 57dB and draws 2.2mA from the 0.5V supply.