0.3 to 1.5V embedded SRAM with device-fluctuation-tolerant access-control and cosmic-ray-immune hidden-ECC scheme

A device-fluctuation-tolerant access-control scheme and a unique cosmic-ray-immune hidden-ECC scheme are implemented in a 32kB SRAM in a 0.13 /spl mu/m CMOS process. The SRAM operates at 0.3V at 6.8MHz under severe device fluctuations. Operation ranges from 30MHz at 0.4V to 960MHz at 1.5V. The hidden-ECC reduces access-timing and the calculated soft-error-rate is reduced by 3.6/spl times/10/sup 10/ per MB.