An 18.5ns 128MB SOI DRAM with a floating body cell

A dynamic latch sense amplifier/bit line replenishes "1" cells with holes lost during word line cycles and reduces the refresh busy rate. A multi-averaging method of dummy cells over 128 pairs of "1s" and "0s" enhances the sense margin and contributes to the 18.5ns access time. The 25.7ns virtually static RAM (VSRAM) mode is realized by taking advantage of the cell's quasi non-destructive read-out.