An ultra-low-power fast-lock-in small-jitter all-digital DLL

Using binary-weighted differential-delay cells and an asynchronous binary search circuit, the proposed 1.0V 0.25 /spl mu/m all-digital DLL achieves nearly 2 orders of magnitude reduction in power consumption, a 36% reduction in jitter, and a 33% reduction in locking cycles, compared to conventional fast-lock mixed-mode DLL.