A 15mW 3.125GHz PLL for serial backplane transceivers in 0.13 /spl mu/m CMOS

A 3.125GHz PLL fabricated in a 0.13 /spl mu/m CMOS process in a area of 0.064mm/sup 2/ is described. The PLL uses an architecture optimized for low noise, low power and small die area. In steady-state operation, the PLL forces the up and down currents in the charge pump to match one another. The total measured jitter is 1.3ps rms when operating at 3.125GHz and the chip consumes 15mW.