The multi-threaded, parity-protected 128-word register files on a dual-core Itanium/sup /spl reg//-family processor

The dual-thread 18-port 128w/spl times/82b FPU register file, and the 22-port 128w/spl times/65b integer register file of the microprocessor is described. Parity embedded into each register provides soft error detection. The design integrates a charge-compensated thread switch and power-saving features to operate at 1.1V consuming 400mW at maximum frequency.