Session 20 overview - processor building blocks

CMOS technology shows every sign of sustaining the capability of providing functional and reliable transistors far below 70nm channel length. However, utilizing this capability for higher integration levels and larger chips requires solutions to a number of challenges, including increased power consumption, increased sub-threshold and gate leakage currents, and increased interconnect RC delay. This session includes seven papers describing low-power high-performance circuit techniques for processor building blocks. Blocks that are discussed include multipliers, adders, and register-file storage arrays. Intra-chip communication is also a critical component in leveraging the speed and performance of these functional units. The final paper of the session proposes a differential-signaling scheme as an alternative to classic repeater-based wiring.