A 200/spl times/160 pixel CMOS fingerprint recognition SoC with adaptable column-parallel processors

A CMOS fingerprint recognition SoC with embedded column-parallel processors is optimized for 2D digital image processing. The processor employs self-configuration features for adaptive filter operations and the pixel includes a sensing block, ADC and frame memory without area penalty. The total image processing time is less than 360 ms at 10 MHz.